Keunho Choi
My office at LG today is located at the inside of a huge FAB plant – just like my office at the STEMCO, my former workplace. In many ways, these speak for my job – I am a plant problem solver. I handle defects. I troubleshoot manufacturing equipment. And I also optimize our processes and operations. Likewise, I am often found in a dust-proof suit working close to 50 hours/week alongside the plant people.
That is, I am like a chef who is responsible for a kitchen. However, unlike a chef who also gets to develop never-tried-before recipes, my job is limited to fixing and improving the existing ones, which of course are crucial, and I did make close to 70 improvements in the last six years. And the joy of solving problems for our people and products that go into iPhone, iPad, PC, server and automobile more than make up for all-nighters and odd shifts. All these efforts also got recognized by LG and I won a prestigious award in merely one year. However, I now want to develop recipes as well. And for this, I must study the underlying fundamental theories and how they mean in the actual field. As such, I am knocking on your door. You will have a student with a long list of questions – right from the field.
"Figure 1: LG Innotek factory in South Korea"
"Figure 2: Me holding a substrate after Laser Direct Imaging"
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Growing up in the 2000s and 2010s- a period of rapid advancements in mobile devices and computers- I became fascinated with the technologies that make people's lives more efficient. This passion naturally led me to pursue a career as an engineer focusing on the functionality, manufacturing methods, and technologies behind the components inside these devices. My role as a production engineer allowed me to collaborate with various departments such as research labs and product development teams, leading me to recognize that my true calling lies in research.
After earning my bachelor's degree in chemical engineering, I began my career at STEMCO, producing Chip on Film (COF), a flexible substrate used to connect display panels and PCBs with Display Driver IC (DDI). In this role, I faced various engineering challenges, especially in managing and optimizing etching and stripping processes. Early on, I took full responsibility for the manufacturing equipment, identifying and resolving defects to improve yield. This experience not only enhanced my problem-solving skills but also helped me grow into an engineer capable of independently leading new initiatives and driving process innovations.
"Figure 3: STEMCO factory in South Korea"
"Figure 4: 1-Metal COF From STEMCO" [1]
Driven to engage with more cutting-edge technologies in the growing packaging industry, I transitioned to LG Innotek, a leader in packaging substrate manufacturing. Within my first year, I led modifications to photo-resist stripping equipment for the electroplating of Copper Pillar Bump Pads on substrates, which required significantly thicker copper layers than general bump pads. My contributions were instrumental to the project’s success, earning me recognition and an award from LG. Since then, LG has implemented this process to enter new markets for copper pillar bump products, unlocking future profit potential.
A key achievement was adapting the stripping system to handle a 168μm thick dry film—six times its original capacity—by reprogramming the conveyor to implement a Stop & Go method. This innovative approach in PCB chemical processing dramatically extended stripping time and eliminated the need for dedicated stripping equipment, saving an estimated $2.6 million in potential acquisition costs.
To achieve this, I adjusted the stripping solution spray at the beginning of the stripping stage to concentrate spray on the same location, maximizing the creation of small perforations on the photoresist surface early in the process, which significantly increased the reaction surface area between the photoresist and stripping chemicals. Additionally, temporarily pausing the conveyor allowed the product to remain in the stripping zone longer than the minimum conveyor speed typically allowed, ensuring complete residue removal.
While this solution successfully increased stripping time, it also introduced new challenges, such as spray marks on the copper surface and insufficient drying that led to staining. I identified that the spray marks were caused by changes in copper roughness due to high-pressure spray during conveyor stops. After extensive experimentation, I discovered that allowing the conveyor to run at a constant speed, once most of the thick photoresist had been removed, combined with lowering the spray pressure, effectively prevented the spray marks. Although the project was a success, I realized that many of the phenomena observed during the process could not be fully explained through experimental methods alone. This realization strengthened my desire to take a research-oriented approach to solving engineering challenges.
"Figure 5: Example of Copper Pillar Bumps
(Copper Pillars on Die)" [2]
"Figure 6: Modification of Photo-resist Stripping Machine for High-thickness Photo-resist"
"Figure 7: RF-System in Package Substrate
from LG Innotek" [3]
I am passionate about processing and aim to combine my background in chemical engineering, six years of experience in product processing, and the advanced knowledge of materials I plan to acquire. In particular, I aspire to conduct in-depth research focusing on the manufacturing and processing of materials utilized in semiconductors and packaging. My goal is to develop phenomenological models that identify the root causes of process-related issues, offering valuable insights to enhance material performance and improve process design.
Furthermore, as the sole lithography engineer on the development team at LG Innotek, I worked on Broadcom’s high-bandwidth network switching device prototypes, designed for next-generation data centers and cloud computing environments. This role provided me with hands-on involvement in the process and allowed me to gain advanced expertise in package substrate manufacturing. I found the experience incredibly rewarding, especially as we successfully passed the final reliability test. In our small team, I was responsible not only for lithography tasks but also for troubleshooting a wide range of issues across the team. One of my key achievements was reducing the PTH (Plated Through Hole) pitch from 350 µm to 150 µm by leveraging a Multi-Layered Core (MLC) structure, enabling a more compact circuit design. However, during the development process, I encountered various technical challenges related to materials, such as delamination and warpage.
For instance, we selected resin-coated copper foil for the build-up layers instead of Ajinomoto Build-up Film (ABF), leveraging recent advancements that reduce dielectric loss. This choice allowed us to successfully develop a high-layer-count structure exceeding 20 layers. However, we encountered significant delamination issues at the copper/epoxy interface. Initially, we hypothesized that the delamination was due to design flaws in degassing, especially in stress-prone areas lacking degassing holes. Although our team optimized the circuit design using warpage simulation tools, these efforts did not produce the desired results.
"Figure 8: Flip-Chip Ball Grid Array Substrate
from LG Innotek" [4]
"Figure 9: Delamination between copper circuit layer and dielectric layer"
As an alternative, I suggested that the high moisture content in the resin might be causing delamination during the thermal treatment process. Observing that a combination of wet processes and reduced curing time—due to the shortened lead time—resulted in moisture accumulating in the epoxy, I suggested this as a key factor contributing to the delamination observed after multiple heat treatments post-lamination.
To test this hypothesis, I introduced a baking process both before and after the pretreatment step for laminating. The results confirmed that baking before pretreatment effectively resolved the issue, completely eliminating delamination. As a result, the project successfully passed the Thermal Stress Test.
Despite resolving the delamination issue, I recognized that it could reoccur depending on the circuit design, and warpage issues remained unresolved. This experience made me increasingly aware of the limitations of current dielectric materials, and I became confident that by improving the adhesion between copper and dielectric layers could significantly enhance substrate performance to meet the demands of the AI computing era, which requires higher layer counts.
Through these experiences, I realized that my true passion lies in researching functional materials for microelectronics and in advancing my career by contributing to innovations that shape the future of the industry.
In addition to my projects, my yield improvement experiences have highlighted the importance of precise material analysis for interpreting defects. This has driven me to pursue research in material characterization using advanced tools like 4D STEM. My goal is to develop new electronic materials for semiconductors, leveraging my career expertise.
"Figure 10: Image of NVIDIA H100 GPU utilizing advanced packaging technology" [5]
If I am to be granted that precious lifetime opportunity to pursue my studies at my dream school, I have absolutely no doubt in my mind that I can achieve all that I set out to achieve due to a set of assets that I have.
Besides gaining mastery of SEM equipment, I gained A to Z problem-solving skills as I experienced making something out of nothing (starting with raw materials). Likewise, I am very comfortable in developing a master plan (which gave me that big picture perspective) and executing (I can budget, calculate necessary human power, can come up with a list of equipment needed and so forth). That is, I can handle A to Z of an experiment.
Moreover, I am taking with me many stories to share – stories from the field because for the last six years, I literally “lived” in plants. I ate with the plant people. I worked side-by-side with them to troubleshoot problems. We also prepared for any scenario because if there is anything I learned is that anything can go wrong in a field.
And I also tasted a bit of how studying the theories can help in the field per se. At the STEMCO & LG Innotek, for instance, I detected numerous defects in Dry Film Laminating, Exposure, Developing, Stripping and Etching processes as a Lithography Process Engineer. Although never more often than not, the answer is in the field, still there were some instances when I studied back in my office to apply what I learned from the theories to find out that they worked – these were indeed the most satisfying moments when I realized once again how it is essential to really understand the underlying to solve real-life problems.
Along the way, I learned to classify problems (close to 1,000) and to customize solutions accordingly. I also left behind many manuals for my colleagues so that they wouldn’t have to struggle as much.
"Figure 11: Posing to celebrate the successful development of an MLC-Structured FC-BGA"
"Figure 12: My teammates and I strengthening bonds through soccer"
Last but never least, teamwork is something I am very comfortable with. As I had to work with so many diverse people, I can work with complex interpersonal relations when interests clash, for instance. And tricky sensitive situations, I am used to them because I always had to walk on a thin line per se to not come across as someone who is there to audit, monitor and check on the plant people. Likewise, I learned how to motivate, how to communicate just right (so that they would trust me and accept me as someone who is there to help). But at the same time, I learned to say no when necessary. As such, maintaining that near-perfect balance is what I learned. Just the same way, I really look forward to working very effectively with my future lab mates at my dream school.
References
1. Figure 4: 1-Metal COF from STEMCO
2. Figure 5: Example of Copper Pillar Bumps (Copper Pillars on Die)
Faraday Technology Corporation, www.faraday-tech.com/en/content/Product/ASIC_Service/Cu-pillarBumping
3. Figure 10: RF-System in Package Substratefrom LG Innotek
LG Innotek, www.lginnotek.com/product/ss/01/list.do?package
4. Figure 10: Flip-Chip Ball Grid Array Substratefrom LG Innotek
LG Innotek, www.lginnotek.com/product/ss/01/list.do?package
5. Figure 10: Image of NVIDIA H100 GPU utilizing advanced packaging technology
Chips and cheese, www.chipsandcheese.com/p/nvidias-h100-funny-l2-and-tons-of-bandwidth